1. Field of the Invention
The present invention generally relates to a semiconductor device and, more specifically, to an MOS type semiconductor device wherein a gate electrode of one transistor is directly connected to an impurity diffusion layer of adjacent transistor. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
A structure in which a gate electrode of one MOS transistor is electrically connected to a source or drain region of another, adjacent transistor has been used in a semiconductor memory device, such as an SRAM. Such a structure is employed to enable electrical connection while improving the degree of integration. More specifically, a polycrystalline silicon film providing the gate electrode of one transistor is used as an interconnection, which interconnection is directly connected to a source or drain region of another, adjacent transistor, whereby the degree of integration is improved.
FIG. 8 is a cross sectional view of a conventional semiconductor device having such a structure.
Referring to FIG. 8, an isolation insulating film 2 which serves as an element isolating region is formed at a main surface of a semiconductor substrate 1 of silicon single crystal. In an element region surrounded by isolation insulating film 2, an MOS transistor 3 is formed. MOS transistor 3 includes impurity diffusion layers 4a and 4b which will be the source and drain regions, formed in the main surface of semiconductor substrate 1. MOS transistor 3 includes a gate electrode 6a formed on semiconductor substrate 1 with a gate oxide film 5 interposed. Gate electrode 6a includes two layers, that is, first polycrystalline silicon film 7a and a second polycrystalline silicon film 8a. Next to MOS transistor 3, an adjacent MOS transistor is formed, which includes a gate electrode 6b consisting of two layers, that is, a first polycrystalline silicon film 7b and a second polycrystalline silicon film 8b. An end portion of the second polycrystalline silicon film 8b of the adjacent MOS transistor extends and is in contact with one impurity diffusion layer 4b of MOS transistor 3. The portion where impurity diffusion layer 4b is in contact with the second polycrystalline silicon 8b is referred to as a direct contact region 9.
The method of manufacturing the conventional semiconductor device above will be described. Referring to FIG. 9, isolation insulating film 2 is formed by using LOCOS method at the main surface of semiconductor substrate 1. On the entire surface of semiconductor substrate 1, a gate oxide film 5 is formed by thermal oxidation. Thereafter, on the entire surface of semiconductor substrate 1, a conductive first polycrystalline silicon film 7 doped with an impurity is deposited.
Referring to FIG. 10, by using a resist pattern 10 patterned by photolithography as a mask, an underlying first polycrystalline silicon film 7 is selectively removed by etching, for example by ion etching. By this etching removal, part of the gate oxide film 5 is exposed at the same time, as shown in the figure.
Referring to FIGS. 10 and 11, resist pattern 10 is removed. By wet etching using hydrofluoric acid, the exposed portion of gate oxide film 5 is removed. By this step, direct contact region 9 is formed. At this time, as will be described later, water marks 30 are formed on a surface of second polycrystalline silicon film 7.
Referring to FIG. 12, on the entire surface of semiconductor substrate 1, a conductive second polycrystalline silicon film 8 doped with an impurity is deposited. On the second polycrystalline silicon film 8, a photoresist film is formed, which is patterned by photolithography, and thus a resist pattern 11 is formed.
Referring to FIGS. 12 and 13, using resist pattern 11 as a mask, the second polycrystalline silicon film 8 and the first polycrystalline silicon film 7 are selectively removed by etching, by ion etching. Consequently, a gate electrode 6a consisting of the first polycrystalline silicon film 7a and the second polycrystalline silicon film 8a formed thereon, as well as a gate electrode 6b consisting of the first polycrystalline silicon film 7b and the second polycrystalline silicon film 8b formed thereon are provided. Patterning of the second polycrystalline silicon film 8 is performed such that an extended portion of the second polycrystalline silicon film 8b is left on the contact region 9 as shown in the figure.
After removal of resist pattern 11, an impurity is introduced from above semiconductor substrate 1 by ion implantation. Thereafter, by thermal processing, impurity diffusion layers 4a and 4b of MOS transistor 3 are formed. In this thermal processing, impurity diffuses also from the second polycrystalline silicon film 8b formed in contact with the surface of semiconductor substrate 1 into semiconductor substrate 1. Diffused impurity and implanted impurity are integrated, forming impurity diffusion layer 4b which comes to be directly in contact with gate electrode 6b at direct contact region 9. Thereafter, through prescribed processes, a semiconductor device is completed. The conventional semiconductor device manufactured through the above described steps suffers from the following problem.
Namely, when the gate oxide film 5 is selectively removed by etching and direct contact region 9 is formed as shown in FIG. 11, the semiconductor substrate 1 is subjected to wet etching using hydrofluoric acid. At this time the first polycrystalline silicon film 7 serving as the etching mask is exposed to the etchant and after drying, water marks are generated on its surface. Water marks 30 are of silicon oxide including a compound of Si, O.sub.2 and H.sub.2 O, which marks are left as stripe-shaped stain after drying. The water marks function as a mask for etching when gate electrodes 6a and 6b are formed by patterning in the steps shown in FIGS. 12 and 13, which may possibly cause pattern defects in gate electrodes 6a and 6b.
A method of using dry etching which does not generate any water mark is also known as a method of etching removal of gate oxide film 5. However, dry etching damages silicon substrate 1, causing degradation of device characteristics.